Every day, several quintillion bytes of data may be generated around the world. This data may come from posts to social media sites, online videos, financial transactions, sensory information gathered by sensors around the world, etc. This vast amount of data is generally stored and maintained in storage nodes, such as solid-state storage drives (SSDs), and the like, which may reside on local networks or on internet-accessible storage. This stored data may then undergo further processing, such as search, encryption/decryption, compression/decompression, and/or other processes. In a server platform, for example, a processing device, such as a central processing unit (CPU), performs operations on the data. The data may be read from the SSD, processed by the CPU, and the processed data may be sent to the source of a request.
The SSD may include non-volatile memory (e.g., flash memory) for storage of data and a controller that facilitates the transfer of data to and from the non-volatile memory. The controller may be capable of queuing multiple read and write command requests from a host (e.g., a server). As such, the controller may send more than one request at a time to the non-volatile memory, thus, improving the overall performance of the SSD. The controller reads/writes data from/to the non-volatile memory through a number of channels. The non-volatile memory may comprise a plurality of memory devices (e.g., NAND devices) that are organized as groups of devices, where each group of memory devices is connected to a corresponding one of the controller channels.
When a controller channel services a read/write request (i.e., an input/output or I/O request), concurrent access to any of the memory devices from the same occupied channel is not possible. That is, when one memory device at a channel is being used in an I/O operation, all other memory devices on that same channel remain idle until the I/O operation is complete. This idle time presents an overhead for the controller that directly affects the performance and latency of the SSD.
The above information disclosed in this Background section is only for enhancement of understanding of the invention, and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.